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ds07-13510-2e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16f mb90f244 mb90f244 n description the mb90f244 is a 16-bit microcontroller optimized for applications in mechatronics such as hdd units. the architecture of the mb90f244 is based on the mb90242a, and embedded with a 128-kbyte flash memory. the instruction set is based on the at architecture of the f 2 mc* family, with additional high-level language supporting instruction, expanded addressing modes, enhanced multiplication and division instructions, and improved bit processing instructions. in addition, long-word data can now be processed due to the inclusion of a 32-bit accumulator. the mb90f244 includes a variety of peripherals on chip, such as the device is equipped with 8-channel 8/10-bit a/d converter, uart, 3-channel 16-bit reload timers, 1-channel 16-bit timer, 4-channel 16-bit input capture and 4-channel dtp/external interrupts. differences between the mb90f244 and mb90f243 to meet the 3.3 v 0.3 v power supply voltage are that the power consumption of the mb90f244 is about 10% less than that of the mb90f243 and the operating frequency of the mb90f244 is up to 50 mhz from 32 mhz of the mb90f243. * : f 2 mc stands for fujitsu flexible microcontroller. n package 80-pin plastic tqfp (fpt-80p-m15)
mb90f244 2 n features ? minimum execution time (target): 40.0 ns at 50 mhz oscillation (3.3 v 0.3 v) ? instruction set optimized for controller applications variety of data types: bit, byte, word, long-word expanded addressing modes: 25 types high coding efficiency improvement of high-precision arithmetic operations through use of 32-bit accumulator enhanced multiplication and division instructions (signed arithmetic operations) ? instruction set supports high-level language (c language) and multitasking inclusion of system stack pointer variety of pointers high instruction set symmetry barrel shift instruction stack check function ? improved execution speed: 8-byte queue ? powerful interrupt functions interrupt processing time: 0.64 m s at 50 mhz oscillation priority levels: 8 levels (programmable) external interrupt inputs: 4 channels ? automatic transfer function independent of cpu extended intelligent i/o service: max.15 channels ? 128-kbyte flash memory access time (min.) : 80 ns sector structure of 16k + 512 2 + 7k + 8k + 32k + 64k program/erase operations from both eprom programmer and cpu through built-in flash memory interface circuit built-in programming booster circuit for flash memory ? internal ram: 1.152 kbyte according to mode settings, data stored on ram can be executed as cpu instructions. ? general-purpose ports: max. 63 channels (single-chip mode) max. 38 channels (external bus mode) ? 18-bit timebase timer ? watchdog timer ? uart: 8 bits 1 channel ? 8/16-bit i/o simple serial interface (max. 12.5 mbps): 1 channel ? 8/10-bit a/d converter: analog inputs: 8 channels resolution: 10 bits (switchable to 8 bits/10 bits) conversion time: min. 1 m s conversion result store register: 4 channels ? 16-bit i/o timer 16-bit free-run timer: 1 channel (operating clock: 0.16 m s) 16-bit input capture: 4 channels ? 16-bit reload timer: 3 channels ? low-power consumption modes sleep mode stop mode hardware standby mode ? packages: tqfp-80 (fpt-80p-m15) (for more information about the package, see section n package dimensions.) (continued)
3 mb90f244 (continued) ? pll clock multiple function ? cmos technology ? power supply voltage: 3.3 v 0.3 v or 5.0 v 0.5 v (varies with conditions such as the operating frequency. see section n electrical characteristics.)
mb90f244 4 n pin assignment md1 md0 v cc p65/an5 p67/an7 p66/an6 p63/an3 p62/an2 v ss p61/an1 p60/an0 av ss avrl avrh av cc p47/a23/asr2/tin2 p46/a22/asr1/tin1 p45/a21/asr0/tin0 p44/a20/sck0 p43/a19/sod0 v ss x0 x1 v cc 5 p00/d00/dq0 p01/d01/dq1 p02/d02/dq2 p03/d03/dq3 p04/d04/dq4 p05/d05/dq5 p06/d06/dq6 p07/d07/dq7 p10/d08/dq8 p11/d09/dq9 p12/d10/dq10 p13/d11/dq11 p14/d12/dq12 p15/d13/dq13 p16/d14/dq14 p17/d15/dq15 r s t p 5 7 / a s r 3 / i n t 3 / b y t e p 5 6 / r d / c e p 5 5 / w r l / w r / o e p 5 4 / w r h / w e p 5 3 / h r q p 5 2 / h a k p 5 1 / r d y c l k / r y / b y p 8 2 / i n t 2 / a t g p 8 1 / i n t 1 p 8 0 / i n t 0 p 7 5 / s o d 1 p 7 4 / s i d 1 p 7 3 / s c k 1 p 7 2 / t o t 2 p 7 1 / t o t 1 p 7 0 / t o t 0 / a n 4 h s t m d 2 p 2 0 / a 0 0 / a q 0 p 2 1 / a 0 1 / a q 1 p 2 2 / a 0 2 / a q 2 p 2 3 / a 0 3 / a q 3 p 2 4 / a 0 4 / a q 4 p 2 5 / a 0 5 / a q 5 p 2 6 / a 0 6 / a q 6 p 2 7 / a 0 7 / a q 7 v s s p 3 0 / a 0 8 / a q 8 p 3 1 / a 0 9 / a q 9 p 3 2 / a 1 0 / a q 1 0 p 3 3 / a 1 1 / a q 1 1 p 3 4 / a 1 2 / a q 1 2 p 3 5 / a 1 3 / a q 1 3 p 3 6 / a 1 4 / a q 1 4 p 3 7 / a 1 5 / a q 1 5 p 4 0 / a 1 6 / a q 1 6 p 4 1 / a 1 7 / a q 1 7 p 4 2 / a 1 8 / s i d0 / a q 1 8 (top view) (fpt-80p-m15)
5 mb90f244 n pin description pin no. pin name circuit type function tqfp-80* 62 x0 a crystal oscillator pins (50 mhz) 63 x1 39 to 41 md0 to md2 c operating mode selection input pins connect directly to v cc 5 or v ss . in the flash memory mode, these pins are set to be v id (= 12.0 v) input pins by performing a proper operation. 60 rst b external reset request input pin 42 hst d hardware standby input pin 65 to 72 p00 to p07 e general-purpose i/o port d00 to d07 i/o pins for the lower 8 bits of the external data bus dq0 to dq7 data i/o pins for each operation command this function is valid in the flash memory mode. 73 to 80 p10 to p17 e general-purpose i/o port this function is valid when the external bus 8-bit mode. d08 to d15 i/o pins for the upper 8 bits of the external data bus this function is valid when 16-bit bus mode. dq8 to dq15 data i/o pins for each operation command this function is valid in the flash memory mode. 1 to 8 p20 to p27 f general-purpose i/o port a00 to a07 output pins for the medium 8 bits of the external address bus aq0 to aq7 address input pins for each operation command this function is valid in the flash memory mode. 10 to 17 p30 to p37 f general-purpose i/o port this function is valid when the corresponding bit of the middle address control register specification is port. a08 to a15 output pins for the medium 8 bits of the external address bus this function is valid when the corresponding bit of the middle address control register specification is port. aq8 to aq15 address input pins for each operation command this function is valid in the flash memory mode. 18 p40 f general-purpose i/o port this function is valid when the corresponding bit of the upper address control register specification is port. a16 external address bus output pin of the bit 16 this function is valid when the corresponding bit of the upper address control register specification is address. aq16 address input pin for each operation command this function is valid in the flash memory mode. *: fpt-80p-m15 (continued)
mb90f244 6 pin no. pin name circuit type function tqfp-80* 19 p41 f general-purpose i/o port this function is valid when the upper address control register specification is port. a17 external address bus output pin of the bit 17 this function is valid when the corresponding bit of the upper address control register specification is address. aq17 address input pin for each operation command this function is valid in the flash memory mode. 20 p42 f general-purpose i/o port this function is valid when the corresponding bit of the upper address control register specification is port. a18 external address bus output pin of the bit 18 this function is valid when the corresponding bit of the upper address control register specification is address. sid0 uart #0 data input pin during uart #0 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. aq18 address input pin for each operation command this function is valid in the flash memory mode. 21 p43 g general-purpose i/o port this function is valid when the uart #0 data output is disabled and the corresponding bit of the upper address control register specification is port. a19 external address bus output pin of the bit 19 this function is valid when the uart #0 data output is disabled and the corresponding bit of the upper address control register specification is address. sod0 uart #0 data output pin this function is valid when the uart #0 data output is enabled. 22 p44 g general-purpose i/o port this function is valid when the uart #0 clock output is disabled and the corresponding bit of the upper address control register specification is port. a20 external address bus output pin of the bit 20 this function is valid when the uart #0 clock output is disabled and the corresponding bit of the upper address control register specification is address. sck0 uart #0 clock i/o pin *: fpt-80p-m15 (continued)
7 mb90f244 pin no. pin name circuit type function tqfp-80* 23 p45 g general-purpose i/o port this function is valid when the corresponding bit of the upper address control register specification is port. a21 external address bus output pin of the bit 21 this function is valid when the corresponding bit of the upper address control register specification is address. asr0 16-bit input capture #0 data input pin during 16-bit input capture #0 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. tin0 16-bit timer #0 data input pin during 16-bit timer #0 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 24 p46 g general-purpose i/o port this function is valid when the corresponding bit of the upper address control register specification is port. a22 external address bus output pin of the bit 22 this function is valid when the corresponding bit of the upper address control register specification is address. asr1 16-bit input capture #1 data input pin during 16-bit input capture #1 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. tin1 16-bit timer #1 data input pin during 16-bit timer #1 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 25 p47 g general-purpose i/o port this function is valid when the corresponding bit of the upper address control register specification is port. a23 external address bus output pin for the bit 23 this function is valid when the corresponding bit of the upper address control register specification is address. asr2 16-bit input capture #2 data input pin during 16-bit input capture #2 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. tin2 16-bit timer #2 data input pin during 16-bit timer #2 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. *: fpt-80p-m15 (continued)
mb90f244 8 pin no. pin name circuit type function tqfp-80* 53 p51 h general-purpose i/o port this function is valid when the ready function is disabled. rdy ready input pin this function is valid when the ready function is enabled. 54 p52 h general-purpose i/o port this function is valid when the hold function is disabled. hak hold acknowledge output pin this function is valid when the hold function is enabled. 55 p53 h general-purpose i/o port this function is valid when the hold function is disabled. hrq hold request input pin this function is valid and when the hold function is enabled. 56 p54 f general-purpose i/o port this function is valid in external bus 8-bit mode, or when wrh pin output is disabled. wrh write strobe output pin for the upper 8 bits of the data bus this function is valid in modes where the external bus 16-bit mode is enabled, and wrh pin output is enabled. we write enable input pin this function is valid in the flash memory mode. 57 p55 f general-purpose i/o port this function is valid when wrl pin output is disabled. wrl / wr write strobe output pin for the lower 8 bits of the data bus this function is valid wrl pin output is enabled. oe output enable input pin for each operation command this function is valid in the flash memory mode. 58 p56 f general-purpose i/o port rd read strobe output pin for the data bus ce chip enable input pin for each operation command this function is valid in the flash memory mode. 59 p57 f general-purpose i/o port asr3 16-bit input capture #3 data input pin during 16-bit input capture #3 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. int3 dtp/external interrupt #3 data input pin during dtp/external interrupt #3 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. byte byte access control input pin this function is valid in the flash memory mode. *: fpt-80p-m15 (continued)
9 mb90f244 pin no. pin name circuit type function tqfp-80* 30, 31, 33, 34, 35, 36, 37 p60, p61, p62, p63, p66, p67, p65 i n-ch open-drain type i/o ports when bits corresponding to the ader are set to 0, reading instructions other than the read-modify-write group returns the pin level. the value written on the data register is output to this pin directly. an0, an1, an2, an3, an6, an7, an5 8/10-bit a/d converter analog input pins use this function after setting bits corresponding to the ader to 1 and setting corresponding bits of the data register to 1. 43 p70 j general-purpose i/o port this function is valid when the bit corresponded to ader is set to 0 and also the output of 16-bit timer #0 is disabled. tot0 16-bit timer output pin this function is valid when the bit corresponded to ader is set to 0 and also the output of 16-bit timer #0 is enabled. an4 8/10-bit ad converter analog input pin this function can be used when the bit corresponded to ader is set to 1 and also the bit correponded to the data resister is set to 1. 44, 45 p70, p72 g general-purpose i/o port this function is valid when the reload timer #1, and #2 output is disabled. tot1, tot2 16-bit timer output pins this function is valid when the 16-bit timer #1, and #2 output is enabled. 46 p73 g general-purpose i/o port this function is valid when the ssi #1 clock output is disabled. sck1 ssi #1 clock output i/o pin 47 p74 g general-purpose i/o port this function is always valid. sid1 ssi #1 data input pin during ssi #1 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 48 p75 g general-purpose i/o port this function is valid when the ssi #1 data output is disabled. sod1 ssi #1 data output pin this function is valid when the ssi #1 data output is disabled. *: fpt-80p-m15 (continued)
mb90f244 10 (continued) pin no. pin name circuit type function tqfp-80* 49, 50 p80, p81 g general-purpose i/o port this function is always valid. int0, int1 dtp/external interrupt input pin when external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 51 p82 g general-purpose i/o port this function is always valid. int2 dtp/external interrupt input pin when external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. because an input to this pin is clamped to low when the cpu stops, use int0 or int1 to wake up the system from the stop mode. at g 8/10-bit a/d converter trigger input pin when 8/10-bit a/d converter is waiting for activation, this input may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. 52 clk g clk output pin ry/by open-drain pin output ready/busy signal in the program deleting operation this function is valid in the flash memory mode. 38 v cc power supply digital circuit power supply pin 64 v cc 5 power supply power supply voltage (5.0 v) input pin for flash memory 9, 32, 61 v ss power supply digital circuit power supply (gnd) pin 26 av cc power supply analog circuit power supply pin this power supply must only be turned on or off when electric potential of av cc or greater is applied to v cc . 27 avrh power supply 8/10-bit a/d converter external reference voltage input pin this pin must only be turned on or off when electric potential of avrh or greater is applied to av cc . 28 avrl power supply 8/10-bit a/d converter external reference voltage input pin 29 av ss power supply analog circuit power supply (gnd) pin *: fpt-80p-m15
11 mb90f244 n i/o circuit type (continued) type circuit remarks a?50 mhz ? oscillation feedback resistor: approximately 1 m w b ? cmos-level hysteresis input (without standby control) ? pull-up resistor: approximately 50 k w c ? cmos-level input ? high voltage control for flash memory testing d ? cmos-level hysteresis input (without standby control) clock halt clock input x0 x1 r r p-ch tr n-ch tr cmos digital input diffusion resistor control signal mode input diffusion resistor digital input p-ch tr cmos n-ch tr diffusion resistor
mb90f244 12 (continued) (continued) type circuit remarks e ? cmos-level output ? ttl-level input (with standby control) f ? cmos-level output ? cmos-level hysteresis input ? ttl-level input (flash memory mode) (with standby control) g ? cmos-level output ? cmos-level hysteresis input (with standby control) h ? cmos-level output ? ttl-level input (with standby control) digital output digital input diffusion resistor flash memory mode standby control signal digital output flash memory input ttl ttl digital output digital input digital output flash memory input ttl cmos flash memory mode standby control signal diffusion resistor digital input digital output cmos digital output diffusion resistor standby control signal digital input digital output digital output ttl diffused resistor standby control signal
13 mb90f244 (continued) type circuit remarks i ? n-ch open-drain cmos-level output ? cmos-level hysteresis input (analog input) (with analog input control) j ? n-ch open-drain cmos-level output ? cmos-level hysteresis input (analog input) (with analog input control) analog input control digital input digital output analog input cmos diffusion resistor digital input digital output analog input cmos digital output analog input control diffusion resistor
mb90f244 14 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to the input or output pins other than medium-and high-voltage pins or if higher than the voltage which shown on 1. absolute maximum ratings in section n electrical characteristicsis applied between v cc and v ss . when latchup occurs, power supply current increases rapidly might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. in addition, for the same reasons take care to prevent the analog power supply from exceeding the digital power supply. 2. treatment of unused pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistors. 3. precautions when using an external clock when an external clock is used, drive x0 only. 4. power supply pins when there are several v cc and v ss pins, those pins that should have the same electric potential are connected within the device when the device is designed in order to prevent misoperation, such as latch-up. however, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards. in addition, give a due consideration to the connection in that current supply be connected to v cc and v ss with the lowest possible impedance. finally, it is recommended to connect a capacitor of about 0.1 m f between v cc and v ss near this device as a bypass capacitor. for example an external clock x0 x1
15 mb90f244 5. crystal oscillation circuit noise in the vicinity of the x0 and x1 pins will cause this device to operate incorrectly. design the printed circuit board so that the bypass capacitor connecting x0 and x1 pins and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible. in addition, because printed circuit board artwork in which the area around the x0 and x1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended. 6. sequence for applying the a/d converter power supply and the analog inputs always be sure to apply the digital power supply (v cc ) before applying the a/d converter power supply (av cc , avrh, and avrl) and the analog inputs (an0 to an7). in addition, when the power is turned off, turn off the a/d converter power supply and the analog inputs first, and then turn off the digital power supply. (turning on or off the analog and digital power supplies simultaneously will not cause any problems.) whether applying or cutting off the power, be certain that avrh does not exceed av cc . 7. external reset input to reliably reset the controller by inputting an l level to the rst pin, ensure that the l level is applied for at least five machine cycles. 8. hst pin when turning on the system, be sure to set the hst pin to h level. never set the hst pin to l level while the rst pin is in l level. 9. clk pin x1 x0 note: clk pin cannot use as i/o port. care must be taken that this is different from standard specification for f 2 mc-16f family. ex. 50 mhz clk stop divide by 2 circuit to internal blocks stop
mb90f244 16 10.specifed interrupt sequence when the interrupt stack area is allocated to the external memory, even if the higher priority level interrupt may generate while the former interrupt is waiting in the stack area, the latter higher priority level interrupt routine has to wait untill the former interrupt routine is excuted. in this case the former interrupt routine is excuted in the latter higher priority level. a b c c aa a b interrupt level (ilm = 0) interrupt level (ilm = 1) interrupt level (ilm = 7) normal interrupt sequence specified interrupt sequence b interrupt generation b interrupt generation c interrupt generation c interrupt generation program operation program transition (resister stack) a: main routine operation (ilm = 7) b: priority 0 interrupt routine (ilm = 0) c: priority 1 interrupt routine (ilm = 1)
17 mb90f244 n block diagram uart sck0 sid0 sod0 sck1 sid1 sod1 av cc avrh avrl av ss an0 to an7 at g 8/16-bit i/o simple serial interface 16-bit timer 16-bit input capture (icu) 4 channels 8/10-bit a/d converter asr0 to asr3 tin0/tot0 to tin2/tot2 p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p51 to p57 p60 to p63 p65 to p67 p70 to p75 p80 to p82 i/o port 63 external bus interface f 2 mc-16f cpu ram flash memory interface flash memory clock controller 16-bit reload timer dtp/external interrupt 4 channels i n t e r n a l d a t a bu s d00 to d15 a00 to a23 clk rdy hak hrq wrh wrl /wr rd x0 x1 rst hst md0 to md2 int0 to int3 dq0 to dq15 aq0 to aq18 we oe ce byte ry/by v cc 5 pll other pins v cc , v ss
mb90f244 18 n f 2 mc-16l cpu programming model dedicated registers al ah accumulator user stack pointer system stack pointer processor status program counter user stack upper limit register system stack upper limit register user stack lower limit register system stack lower limit register direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register usp ssp ps pc uspcu sspcu uspcl sspcl dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits general-purpose registers r7 r5 r3 r1 000180 h + (rp 10 h ) r6 r4 r2 r0 rw3 rw2 rw1 rw0 rl3 rl2 rl1 rl0 max. 32 banks 16 bits processor status (ps) ilm rp i s t n z v c ccr
19 mb90f244 n memory map single-chip mode ffffff h internal rom/ external bus mode fe0000 h 00057f h 000100 h 0000c0 h 000020 h 000000 h external rom/ external bus mode flash memory rom flash memory rom ram ram ram i/o i/o i/o peripheral peripheral peripheral : access inhibited : internal access memory : exernal access memory
mb90f244 20 n i/o map (continued) address register name register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxC b 000006 h pdr6 port 6 data register r/w port 6 111C1111 b 000007 h pdr7 port 7 data register r/w port 7 C C xxxxxx b 000008 h pdr8 port 8 data register r/w port 8 CCCCCxxx b 000009 h to 00000f h (vacancy) 000010 h ddr0 port 0 data direction register r/w port 0 00000000 b 000011 h ddr1 port 1 data direction register r/w port 1 00000000 b 000012 h ddr2 port 2 data direction register r/w port 2 00000000 b 000013 h ddr3 port 3 data direction register r/w port 3 00000000 b 000014 h ddr4 port 4 data direction register r/w port 4 00000000 b 000015 h ddr5 port 5 data direction register r/w port 5 0000000C b 000016 h ader analog input enable register r/w analog input enabled 11111111 b 000017 h ddr7 port 7 data direction register r/w port 7 C C 0 0 0 0 0 0 b 000018 h ddr8 port 8 data direction register r/w port 8 CCCCC000 b 000019 h to 00001f h (vacancy) 000020 h scr1 serial control status register 1 r/w 8/16-bit i/o simple serial interface ch. 1 10000000 b 000021 h ssr1 serial status register 1 r/w CCCCCC00 b 000022 h sdr1l serial data register 1 (l) r/w xxxxxxxx b 000023 h sdr1h serial data register 1 (h) r/w xxxxxxxx b 000024 h to 000027 h (vacancy) 000028 h umc0 mode control register 0 r/w uart ch. 0 00000100 b 000029 h usr0 status register 0 r/w 00010000 b 00002a h uidr0/ uodr0 input data register 0/ output data register 0 r/w xxxxxxxx b 00002b h urd0 rate and data register 0 r/w 0 0 0 0 0 0 0 0 b 00002c h to 00002e h (vacancy)
21 mb90f244 (continued) address register name register read/ write resource name initial value 00002f h ckscr clock selection register r/w pll C C C C 1 1 0 0 b 000030 h enir dtp/interrupt enable register r/w dtp/external interrupt CCCC0000 b 000031 h eirr dtp/interrupt source register r/w CCCC0000 b 000032 h elvr request level setting register r/w 00000000 b 000033 h to 00003f h (vacancy) 000040 h tmcsr0 timer control status register #0 r/w 16-bit timer #0 00000000 b 000041 h r/w CCCC0000 b 000042 h tmr0 16-bit timer register #0 r xxxxxxxx b 000043 h r xxxxxxxx b 000044 h tmrlr0 16-bit reload register #0 w xxxxxxxx b 000045 h w xxxxxxxx b 000046 h (vacancy) 000047 h 000048 h tmcsr1 timer control status register #1 r/w 16-bit timer #1 00000000 b 000049 h r/w CCCC0000 b 00004a h tmr1 16-bit timer register #1 r xxxxxxxx b 00004b h r xxxxxxxx b 00004c h tmrlr1 16-bit reload register #1 w xxxxxxxx b 00004d h w xxxxxxxx b 00004e h (vacancy) 00004f h 000050 h tmcsr2 timer control status register #2 r/w 16-bit timer #2 00000000 b 000051 h r/w CCCC0000 b 000052 h tmr2 16-bit timer register #2 r xxxxxxxx b 000053 h r xxxxxxxx b 000054 h tmrlr2 16-bit reload register #2 w xxxxxxxx b 000055 h w xxxxxxxx b 000056 h to 00005f h (vacancy) 000060 h icp0 input capture register 0 r 16-bit input capture 0 and 1 xxxxxxxx b 000061 h r xxxxxxxx b 000062 h icp1 input capture register 1 r xxxxxxxx b 000063 h r xxxxxxxx b 000064 h ics0 input capture control status register 0 and 1 r/w 00000000 b 000065 h (vacancy)
mb90f244 22 (continued) address register name register read/ write resource name initial value 000066 h icp2 input capture register 2 r 16-bit input capture 2 and 3 xxxxxxxx b 000067 h xxxxxxxx b 000068 h icp3 input capture register 3 r xxxxxxxx b 000069 h xxxxxxxx b 00006a h ics1 input capture control status register 2 and 3 r/w 00000000 b 00006b h (vacancy) 00006c h tcdt timer data register r 16-bit freerun timer 00000000 b 00006d h r 00000000 b 00006e h tccs timer control status register r/w 00000000 b 00006f h (vacancy) 000070 h adcs 1 a/d control status register 1 r/w 8/10-bit a/d converter 000C0000 b 000071 h adcs 2 a/d control status register 2 r/w C 0 0 0C C 0 0 b 000072 h adct 1 conversion time setting register 1 r/w xxxxxxxx b 000073 h adct 2 conversion time setting register 2 r/w xxxxxxxx b 000074 h adtl0 a/d data register 0 (l) r xxxxxxxx b 000075 h adth0 a/d data register 0 (h) r CCCCCCxx b 000076 h adtl1 a/d data register 1 (l) r xxxxxxxx b 000077 h adth1 a/d data register 1 (h) r CCCCCCxx b 000078 h adtl2 a/d data register 2 (l) r xxxxxxxx b 000079 h adth2 a/d data register 2 (h) r CCCCCCxx b 00007a h adtl3 a/d data register 3 (l) r xxxxxxxx b 00007b h adth3 a/d data register 3 (h) r CCCCCCxx b 00007c h to 00008f h (vacancy) 000090 h to 00009e h (system reserved area)* 1 00009f h dirr delayed interrupt source generation/ release register r/w delayed interrupt generation module CCCCCCC0 b 0000a0 h stbyc standby control register r/w low-power consumption mode 0001xxxx b 0000a3 h macr middle address control register w external pin 0000a4 h hacr high address control register w 0000a5 h epcr external pin control register w * 2 * 2 * 2
23 mb90f244 (continued) explanation of read/write r/w : readable and writable r : read only w : write only explanation of initial values 0 : the initial value of this bit is 0. 1 : the initial value of this bit is 1. x: the initial value of this bit is undefined. C : this bit is unused. no initial value is defined. *1: access prohibited. *2: the initial values are changed depending on a bus mode. *3: the only area available for the external access below address 0000ff h is this area. addresses not explained in the table are (reserved area); accesses to these areas are handled accesses to internal areas. no access signal is generated for the external bus. note: do not use any (vacancy). address register name register read/ write resource name initial value 0000a8 h wtc watchdog timer control register r/w watchdog timer xxxxxxxx b 0000a9 h tbtc timebase timer control register r/w timebase timer 0xx00000 b 0000ae h fmcs control status register r/w flash memory 0 0 0 x0C C 0 b 0000b0 h icr00 interrupt control register 00 r/w* 3 interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w* 3 00000111 b 0000b2 h icr02 interrupt control register 02 r/w* 3 00000111 b 0000b3 h icr03 interrupt control register 03 r/w* 3 00000111 b 0000b4 h icr04 interrupt control register 04 r/w* 3 00000111 b 0000b5 h icr05 interrupt control register 05 r/w* 3 00000111 b 0000b6 h icr06 interrupt control register 06 r/w* 3 00000111 b 0000b7 h icr07 interrupt control register 07 r/w* 3 00000111 b 0000b8 h icr08 interrupt control register 08 r/w* 3 00000111 b 0000b9 h icr09 interrupt control register 09 r/w* 3 00000111 b 0000ba h icr10 interrupt control register 10 r/w* 3 00000111 b 0000bb h icr11 interrupt control register 11 r/w* 3 00000111 b 0000bc h icr12 interrupt control register 12 r/w* 3 00000111 b 0000bd h icr13 interrupt control register 13 r/w* 3 00000111 b 0000be h icr14 interrupt control register 14 r/w* 3 00000111 b 0000bf h icr15 interrupt control register 15 r/w* 3 00000111 b 0000c0 h to 0000ff h (external area)* 3
mb90f244 24 n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: v cc 5 must always exceed v cc . *2: av cc , avrh and avrl must not exceed v cc . also avrl must not exceed avrh. *3: v i1 and v o must not exceed v cc + 0.3 v. *4: v i2 must not exceed v cc 5 + 0.3 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 4.0 v v cc 5v ss C 0.3 v ss + 7.0 v *1 av cc v ss C 0.3 v ss + 4.0 v *2 avrh v ss C 0.3 v ss + 4.0 v *2 avrl v ss C 0.3 v ss + 4.0 v *2 input voltage v i1 v ss C 0.3 v cc + 0.3 v *3 v i2 v ss C 0.3 v cc 5 + 0.3 v *4 output voltage v o v ss C 0.3 v cc + 0.3 v *3 l level maximum output current i ol ? 10 ma l level average output current i olav ? 3ma l level total maximum output current s i ol ? 60 ma l level total average output current s i olav ? 30 ma h level maximum output current i oh ? C10 ma h level average output current i ohav ? C3 ma h level total maximum output current s i oh ? C60 ma h level total average output current s i ohav ? C30 ma power consumption p d ? 350 mw operating temperature t a 0+70 c storage temperature tstg C55 +125 c
25 mb90f244 2. recommended operating conditions (av ss = v ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 3.6 v normal operation v cc 3.0 3.6 v maintaining the stop status v cc 54.55.5v operating temperature t a 0+70 c
mb90f244 26 3. dc characteristics (v cc 5 = 5.0 v 0.5 v, v cc = 3.3 v 0.3 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) (continued) parameter symbol pin name condition value unit remarks min. max. h level input voltage v ih2 0.7 v cc v cc 5 + 0.3 v ttl input v ih1s p60 to p63, p65 to p67, p70 0.8 v cc v cc + 0.3 v cmos hysteresis input v ih2s 0.8 v cc v cc 5 + 0.3 v cmos hysteresis input v ih2s5 rst , hst 0.8 v cc 5v cc 5 + 0.3 v cmos hysteresis input v ihm md0 to md2 0.7 v cc 5v cc 5 + 0.3 v cmos input l level input voltage v il2 v ss C 0.3 0.2 v cc vttl input v il1s p60 to p63, p65 to p67, p70 v ss C 0.3 0.2 v cc v cmos hysteresis input v il2s v ss C 0.3 0.2 v cc v cmos hysteresis input v il2s5 rst , hst v ss C 0.3 0.2 v cc 5 v cmos hysteresis input v ilm md0 to md2 v ss C 0.3 0.2 v cc 5vcmos input h level output voltage v oh all ports except port 6 v cc = 3.0 v i oh = C1.6 ma v cc C 0.3 v l level output voltage v ol all ports v cc = 3.0 v i ol = 2.0 ma 0.4v h level input current i ih1 md0 to md2 v cc = 3.6 v v cc 5 = 5.5 v v ih = 0.7 v cc 5 C10 m acmos input i ih2 v cc = 3.6 v v cc 5 = 5.5 v v ih = 2.2 v C10 m attl input i ih3 except port 6, rst , hst v cc = 3.6 v v cc 5 = 5.5 v v ih = 0.8 v cc C10 m a cmos hysteresis input i ih4 p60 to p63, p65 to p67 v cc = 3.6 v v cc 5 = 5.5 v v ih = 0.7 v cc C10 m a cmos hysteresis input only port 6 l level input current i il1 md0 to md2 v cc = 3.6 v v cc 5 = 5.5 v v il = 0.3 v cc 5 10 m acmos input i il2 v cc = 3.6 v v cc 5 = 5.5 v v il = 0.8 v 10 m attl input i il3 except port 6, rst , hst v cc = 3.6 v v cc 5 = 5.5 v v il = 0.2 v cc 10 m a cmos hysteresis input i il4 p60 to p63, p65 to p67 v cc = 3.6 v v cc 5 = 5.5 v v il = 0.3 v cc 10 m a cmos hysteresis input only port 6
27 mb90f244 (continued) (v cc 5 = 5.0 v 0.5 v, v cc = 3.3 v 0.3 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) *1: because the current values are tentative values, they are subject to change without notice due to our efforts to improve the characteristics of these devices. *2: to prevent improper commands from being activated during rise and fall of v cc 5, the internal v cc 5 detection circuit of the flash memory allows only read accesses and ignores write accesses while v cc 5 is lower than v lko . parameter symbol pin name condition value unit remarks min. typ. max. power supply current* 1 i cc1 v cc cpu normal mode at 25 mhz v cc = 3.15 v to 3.6 v 50ma flash memory read state i cc1 v cc v cc = 3.3 v 0.15 v 45ma flash memory read state i cc51 v cc 533ma flash memory read state i cc2 v cc cpu normal mode at 25 mhz v cc = 3.15 v to 3.6 v 50ma flash memory program/erase state i cc2 v cc v cc = 3.3 v 0.15 v 45ma flash memory program/erase state i cc52 v cc 553ma flash memory program/erase state i ccs v cc cpu sleep mode at 25 mhz 20ma i cc5s v cc 55ma i cch v cc cpu stop mode t a = +25 c 100 m a i cc5h v cc 5100 m a input capacitance c in except v cc , v cc 5, v ss 10pf pull-up resistor r pull rst v cc = 3.3 v v cc 5 = 5.0 v 22 220 k w open-drain output leakage voltage i leak por t 6 10 m a low v cc 5 lock voltage* 2 v lko tbd3.6v
mb90f244 28 4. flash memory programming/eraseing characteristics (v cc 5 = 5.0 v 0.5 v, v cc = 3.3 v 0.3 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : the internal automatic algorithm continues operations for up to 48 ms, for each 1-byte writing operation. parameter condition value unit remarks min. typ. max. sector eraseing time t a = +25 c, v cc = 3.3 v, v cc 5 = 5.0 v 1.5 13.5 sec except for the write time before internal erase operation chip eraseing time 27.0 sec except for the write time before internal erase operation byte programmimg time 16 m s except for the over head time of the system chip programming time 2.1sec except for the over head time of the system erase/program cycle 100 cycles
29 mb90f244 5. ac characteristics (1) clock timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) parameter symbol pin name condition value unit remarks min. max. clock frequency f c x0, x1 v cc = 3.15 v to 3.6 v 50 mhz f c x0, x1 v cc = 3.3 v 0.3 v 40 mhz clock cycle time t c x0, x1 1/f c ns input clock pulse width p wh , p wl x0 10 ns input clock rising/falling time t cr , t cf x0 8 ns clock timing relationship between clock frequency and power supply voltage t c 0.7 v cc p wl p wh t cr t cf 0.3 v cc 3.6 p o w e r s u p p l y v o l t a g s e v c c ( v ) operation assurunce range (t a = C0 c to +70 c) 3.15 3.0 40 50 source oscillation clock f c (mhz)
mb90f244 30 (2) clock output timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t c (clock cycle time), see (1) clock timing. (3) reset and hardware standby input (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. note: when hardware standby input is given, the machine cycle is simultaneously selected to be divide-by-32. parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk 2 t c *ns clk - ? clk t chcl clk 1 t cyc /2 C 15 1 t cyc /2 + 15 ns parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 5 t cyc *ns hardware standby input time t hstl hst 5 t cyc *ns t cyc clk 2.0 v 2.0 v 0.8 v t chcl rst hst t rstl , t hstl 0.2 v cc 50.2 v cc 5
31 mb90f244 (4) power-on reset (av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : before the power supply rising, v cc must be lower than 0.2 v. note: the above standards are the values needed in order to activate a power-on reset. parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc , v cc 5 30ms* power supply cut-off time t off v cc , v cc 51ms t r v cc 2.1 v 0.2 v t off 0.2 v 0.2 v v cc 3.3 v 3.0 v v ss if power supply voltage needs to be changed in the course of operation, a smooth voltage rise is recommended by suppressing the voltage variation as shown below. it is recommended that the rate of increase in the voltage be kept to no more than 50 mv/ms. hold ram data
mb90f244 32 (5) bus read timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. parameter symbol pin name condition value unit remarks min. max. address cycle time t acyc an23 to an00 2 t cyc * C 10 ns valid address ? rd time t avrl an23 to an00 1 t cyc */2 C 13 ns rd pulse width t rlrh rd 1 t cyc * C 20 ns rd ? data read time t rldv d15 to d00 1 t cyc * C 30 ns valid address ? data read time t avdv d15 to d00 3 t cyc */2 C 30 ns rd - ? data hold time t rhdx d15 to d00 0 ns rd - ? address valid time t rhax an23 to an00 1 t cyc */2 C 20 ns valid address ? clk - time t avch an23 to an00, clk 1 t cyc */2 C 20 ns rd ? clk time t rlcl rd , clk 1 t cyc */2 C 20 ns clk 2.0 v 0.8 v 2.0 v 0.8 v 0.8 v 2.0 v 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v t rlrh rd an23 to an00 d 15 to d00 t rhax t rlcl t av r l t av c h t rldv t acyc t rhdx t av d v
33 mb90f244 (6) bus write timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. parameter symbol pin name condition value unit remarks min. max. valid address ? wr time t avwl an23 to an00 1 t cyc */2 C 13 ns wr pulse width t wlwh wrl, wrh 1 t cyc * C 20 ns write data ? wr - time t dvwh d15 to d00 1 t cyc * C 33 ns wr - ? data hold time t whdx d15 to d00 1 t cyc */2 C 15 ns wr - ? address valid time t whax an23 to an00 1 t cyc */2 C 15 ns wr - ? clk time t wlcl wrl , wrh , clk 1 t cyc */2 C 20 ns clk wr (wrl , wrh ) an23 to an00 d 15 to d00 write data 0.8 v t wlcl 2.0 v 0.8 v t wlwh t av w l t whax t dvwh 0.7 v 0.2 v 2.0 v 0.8 v 2.0 v 0.8 v 0.7 v 0.2 v t whdx
mb90f244 34 (7) ready input timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) note: if the rdy setup time is insufficient, use the auto ready function. (8) hold timing (v cc = 3.0 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. note: at least one cycle is required from the time when hrq is fetched until hak changes. parameter symbol pin name condition value unit remarks min. max. rdy setup time t ryhs rdy source oscillation 50 mhz 15 38 ns rdy hold time t ryhh rdy 0 38 ns parameter symbol pin name condition value unit remarks min. max. pin floating ? hak time t xhal hak 30 1 t cyc *ns hak time - ? pin valid time t hahv hak 1 t cyc *2 t cyc *ns clk rd /wr rdy an23 to an00 d15 to d00 d15 to d00 2.0 v 2.0 v 0.8 v 0.8 v cc 0.8 v cc t ryhh t ryhs external address wait cycle wait cycle read data write data hrq 2.0 v t xhal hak pins 0.8 v 2.0 v 0.8 v 0.2 v 0.8 v t hahv
35 mb90f244 (9) uart timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. notes: these are the ac characteristics for clk synchronous mode. c l is the load capacitance added to pins during testing. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc for internal shift clock mode output pin, c l = 80 pf 8 t cyc *ns sck ? sod delay time t slov C80 80 ns valid sid ? sck - t ivsh 100 ns sck - ? valid sid hold time t shix 60ns serial clock h pulse width t shsl for external shift clock mode output pin, c l = 80 pf 4 t cyc *ns serial clock l pulse width t slsh 4 t cyc *ns sck ? sod delay time delay time t slov 150 ns valid sid ? sck - t ivsh 60ns sck - ? valid sid hold time t shix 60ns
mb90f244 36 internal shift clock mode external shift clock mode sck0 2.0 v 0.8 v 2.0 v 0.8 v t scyc sod0 sid0 t slov t ivsh t shix 0.8 v sck0 sod0 sid0 0.8 v cc t slsh 2.0 v cc 0.8 v cc 0.8 v cc 2.0 v cc t shsl t slov t ivsh t shix 2.0 v cc 0.8 v cc 2.0 v cc 0.8 v cc 2.0 v cc 0.8 v cc 2.0 v cc 0.8 v cc 2.0 v cc
37 mb90f244 (10) serial i/o timing (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. note: c l is the load capacitance added to pins during testing. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc for internal shift clock mode output pin, c l = 80 pf 2 t cyc *ns sck - ? sod delay time t slov 1 t cyc */2 ns valid sid ? sck - t ivsh C15 ns sck - ? valid sid hold time t shix 1/2 t cyc * ns internal shift clock mode sck1 sod1 sid1 0.8 v t scyc 2.0 v cc 0.8 v cc t ivsh t slov t shix 2.0 v 0.8 v 0.8 v cc 2.0 v cc 0.8 v cc 2.0 v cc
mb90f244 38 (11) timer input timing (v cc = 3.0 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. (12) timer output timing (v cc = 3.0 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t tiwh , t tiwl asr0 to asr3, tin0 to tin2 4 t cyc * ns parameter symbol pin name condition value unit remarks min. max. clk - ? change time t to tot0 to tot2 v cc = 3.3 v 0.3 v 40 ns asr0 to asr3 tin0 to tin2 0.8 v 2.0 v 2.0 v 0.8 v t tiwh t tiwl tot0 to tot2 clk 0.8 v 2.0 v 2.0 v t to
39 mb90f244 (13) trigger input timing (v cc = 3.0 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) * : for information on t cyc (cycle time), see (2) clock output timing. parameter symbol pin name condition value unit remarks min. max. input pulse width t trgh , t trgl at g , int0 to int3 5 t cyc * ns at g int0 to int3 0.8 v cc t trgh 0.2 v cc 0.8 v cc t trgl 0.2 v cc
mb90f244 40 6. a/d converter electrical characteristics (v cc = 3.3 v 0.3 v, v cc 5 = 5.0 v 0.5 v, av ss = v ss = 0.0 v, t a = 0 c to +70 c) *1: when f c = 50 mhz (frequency), and the machine cycle is 4.0 ns. the minimum value of the adct resister is #a224, differs from that of the mb90f243. *2: current when the a/d converter is not operating and the cpu is stopped. notes: the smaller | avrh C avrl |, the greater the error would become relatively. if the output impedance of the external circuit for the analog input is high, sampling period might be insufficient. when the sampling period set at near the minimum value, the output impedance of the external circuit should be less than approximately 300 w. parameter symbol pin name condition value unit remarks min. typ. max. resolution an0 to an3, an5 to an7 8, 10 10 bit an4 8 8 bit total error t.b.d lsb target: 4.0 linearity error t.b.d lsb target: 2.0 differential linearity error t.b.dlsb target: 1.9 zero transition voltage v 0t an0 to an3, an5 to an7 avrl C1.0 lsb avrl +1.0 lsb avrl +4.0 lsb mv v 0t an4 avrl C1.0 lsb avrl +1.0 lsb avrl +1.5 lsb mv 8-bit precision in calculation full-scale transition voltage v fst an0 to an3, an5 to an7 avrh C4.0 lsb avrh C1.0 lsb avrh +1.0 lsb mv v fst an4 avrh C2.0 lsb avrh C1.0 lsb avrh +1.0 lsb mv 8-bit precision in calculation conversion time setup by adct register v cc = 3.3 v 0.3 v* 1 1.00 m s sampling period 440ns conversion period a 120ns conversion period b 120ns conversion period c 200ns analog port input current i ain an0 to an7 0.1 3 m a analog input voltage an0 to an7 avrl avrh v reference voltage avrh avrh C avrl 2.7 avrl + 2.7 av cc v avrl 0 avrh C 2.7 v power supply current i a av cc av cc = 3.3 v 0.3 v 7 9 ma av cc = 3.3 v 0.15 v 7 8 ma i as * 2 av cc = 3.3 v stop mode 5 m a reference voltage supply current i r avrh av cc = 3.3 v stop mode 1.01.5ma i rs * 2 avrh 5 m a interchannel disparity an0 to an3, an5 to an7 4lsb no rating for an4 because of calculated by 8-bit precision 3
41 mb90f244 analog input circuit model diagram note: use the values shows as reference only. analog input pin avrh avrl c o = approx. 60 pf comparator comparator comparator r on1 r on2 approx. 300 w approx. 150 w c 1 approx. 4 pf be switched on, only while a/d conversion is performed.
mb90f244 42 6. a/d converter glossary resolution analog changes that are identifiable with the a/d converter. when the number of bits is 10, analog voltage can be divide into 2 10 . linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error (unit: lsb) the difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, non-linearity error, differential linearity error, and noise digital output 11 1111 1111 11 1111 1110 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 0000 0010 00 0000 0001 00 0000 0000 v ot v nt v (n + 1)t v fst analog input (1 lsb n + v ot ) linearity error 1 lsb = [v] = [lsb] = C 1 lsb [lsb] v ot : voltage for digital output transit from 000 h to 001 h v fst : voltage for digital output transit from 3fe h to 3ff h 1022 v fst C v ot digital output n linearity error 1 lsb v nt C (1 lsb n + v ot ) digital output n differential linearity error 1 lsb v (n+1)t C v nt
43 mb90f244 n instructions (412 instructions) table 1 explanation of items in table of instructions item explanation mnemonic upper-case letters and symbols: represented as they appear in assembler lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. see table 4 for details about meanings of letters in items. b indicates the correction value for calculating the number of actual cycles during execution of instruction. the number of actual cycles during execution of instruction is summed with the value in the cycles column. operation indicates operation of instruction. lh indicates special operations involving the bits 15 through 08 of the accumulator. z: transfers 0. x: extends before transferring. : transfers nothing. ah indicates special operations involving the high-order 16 bits in the accumulator. *: transfers from al to ah. : no transfer. z: transfers 00 h to ah. x: transfers 00 h or ff h to ah by extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). *: changes due to execution of instruction. : no change. s: set by execution of instruction. r: reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: instruction is a read-modify-write instruction : instruction is not a read-modify-write instruction note: cannot be used for addresses that have different meanings depending on whether they are read or written.
mb90f244 44 table 2 explanation of symbols in table of instructions (continued) symbol explanation a 32-bit accumulator the number of bits used varies according to the instruction. byte: low order 8 bits of al word: 16 bits of al long: 32 bits of al, ah ah high-order 16 bits of a al low-order 16 bits of a sp stack pointer (usp or ssp) pc program counter spcu stack pointer upper limit register spcl stack pointer lower limit register pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 compact direct addressing direct addressing physical direct addressing bits 0 to 15 of addr24 bits 16 to 23 of addr24 io i/o area (000000 h to 0000ff h )
45 mb90f244 (continued) symbol explanation #imm4 #imm8 #imm16 #imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel ear eam branch specification relative to pc effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list
mb90f244 46 table 3 effective address fields * : the number of bytes for address extension is indicated by the + symbol in the # (number of bytes) column in the table of instructions. code notation address format number of bytes in address extemsion* 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacemen 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + dip16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
47 mb90f244 table 4 number of execution cycles for each form of addressing * : (a) is used in the cycles (number of cycles) column and column b (correction value) in the table of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles * : (b), (c), and (d) are used in the cycles (number of cycles) column and column b (correction value) in the table of instructions. code operand (a)* number of execution cycles for each from of addressing 00 to 07 ri rwi rli listed in table of instructions 08 to 0b @rwj 1 0c to 0f @rwj + 4 10 to 17 @rwi + disp8 1 18 to 1b @rwj + disp16 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + dip16 @addr16 2 2 2 1 operand (b)* (c)* (d)* byte word long internal register + 0 + 0 + 0 internal ram even address + 0 + 0 + 0 internal ram odd address + 0 + 1 + 2 even address not in internal ram + 1 + 1 + 2 odd address not in internal ram + 1 + 3 + 6 external data bus (8 bits) + 1 + 3 + 6
mb90f244 48 table 6 transfer instructions (byte) [50 instructions] (continued) mnemonic # ~ b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 mov a, @sp+disp8 movp a, addr24 movp a, @a movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 movx a, @sp+disp8 movpx a, addr24 movpx a, @a mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov @sp+disp8, a movp addr24, a mov ri, ear mov ri, eam movp @a, ri mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah 2 3 1 2 2+ 2 2 2 3 3 5 2 1 2 3 2 2 2+ 2 2 2 2 3 3 5 2 2 3 1 2 2+ 2 3 3 5 2 2+ 2 2 2+ 2 3 3 3 3+ 2 2 2 1 1 2+ (a) 2 2 2 6 3 3 2 1 2 2 1 1 2+ (a) 2 2 2 3 6 3 3 2 2 2 1 2 2+ (a) 2 6 3 3 2 3+ (a) 3 3 3+ (a) 2 3 3 2 2+ (a) 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli))+disp8) byte (a) ? ((sp)+disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi))+disp8) byte (a) ? ((rli))+disp8) byte (a) ? ((sp)+disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli)) +disp8) ? (a) byte ((sp)+disp8) ? (a) byte (addr24) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte ((a)) ? (ri) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) z z z z z z z z z z z z z x x x x x x x x x x x x x C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C * * * * * * * * C * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
49 mb90f244 (continued) for an explanation of (a) and (b), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw xch a, ear xch a, eam xch ri, ear xch ri, eam 2 2+ 2 2+ 3 3+ (a) 4 5+ (a) 0 2 (b) 0 2 (b) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90f244 50 table 7 transfer instructions (word) [40 instructions] note: for an explanation of (a) and (c), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw a, @sp+disp8 movpwa, addr24 movpwa, @a movw dir, a movw addr16, a movw sp, # imm16 movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw @sp+disp8, a movpwaddr24, a movpw@a, rwi movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 3 5 2 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2 2 1 1 2+ (a) 2 2 2 3 6 3 3 2 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) 2 3 3+ (a) 4 5+ (a) (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (a) ? ((sp) +disp8 word (a) ? (addr24) word (a) ? ((a)) word (dir) ? (a) word (addr16) ? (a) word (sp) ? imm16 word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word ((sp) +disp8) ? (a) word (addr24) ? (a) word ((a)) ? (rwi) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
51 mb90f244 table 8 transfer instructions (long word) [11 instructions] for an explanation of (a) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw movl a, ear movl a, eam movl a, # imm32 movl a, @sp + disp8 movpl a, addr24 movpl a, @a movpl@a, rli movl @sp + disp8, a movpl addr24, a movl ear, a movl eam, a 2 2+ 5 3 5 2 2 3 5 2 2+ 1 3+ (a) 3 4 4 3 5 4 4 2 3+ (a) 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (a) ? ((sp) +disp8) long (a) ? (addr24) long (a) ? ((a)) long ((a)) ? (rli) long ((sp) + disp8) ? (a) long (addr24) ? (a) long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90f244 52 table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw add a, #imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 3 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 3 2 3 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 3 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) + imm8 byte (a) ? (a) + (dir) byte (a) ? (a) + (ear) byte (a) ? (a) + (eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) C imm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C C C * * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2 3+ (a) 2 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 2 2 3+ (a) 2 3+ (a) 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) + (ear) word (a) ? (a) + (eam) word (a) ? (a) + imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) C imm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C * * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 5 6+ (a) 4 5 6+ (a) 4 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) + imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) C imm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
53 mb90f244 table 10 increment and decrement instructions (byte/word/long word) [12 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 3+ (a) 2 3+ (a) 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 2 3+ (a) 2 3+ (a) 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 4 5+ (a) 4 5+ (a) 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * mnemonic # ~ b operation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 2 2 2+ (a) 2 0 0 (b) 0 byte (ah) C (al) byte (a) C (ear) byte (a) C (eam) byte (a) C imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 2 2 2+ (a) 2 0 0 (c) 0 word (ah) C (al) word (a) C (ear) word (a) C (eam) word (a) C imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 3 4+ (a) 3 0 (d) 0 long (a) C (ear) long (a) C (eam) long (a) C imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
mb90f244 54 table 12 unsigned multiplication and division instructions (word/long word) [11 instructions] for an explanation of (b) and (c), refer to table 5, correction values for number of cycle used to calculate number of actual cycles. *1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. *2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. *3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. *4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. *5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not 0. *9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. *10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not 0. *12: 3 when word (ear) is zero, and 11 when word (ear) is not 0. *13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0. mnemonic # ~ b operation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
55 mb90f244 table 13 signed multiplication and division instructions (word/long word) [11 insturctions] for an explanation of (b) and (c), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. *2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. *3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. *4: when the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. when the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. *5: when the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. when the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. note: which of the two values given for the number of execution cycles applies when an overflow error occurs in a div or divw instruction depends on whether the overflow was detected before or after the operation. mnemonic # ~ b operation lh ah i s t n z v c rmw div a div a, ear div a, eam divw a, ear divw a, eam 2 2 2+ 2 2+ * 1 * 2 * 3 * 4 * 5 0 0 * 6 0 * 7 word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C mul a mul a, ear mul a, eam mulw a mulw a, ear mulw a, eam 2 2 2+ 2 2 2+ * 8 * 9 * 10 * 11 * 12 * 13 0 0 (b) 0 0 (b) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90f244 56 table 14 logical 1 instructions (byte, word) [39 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C * * C C C * * C C C * * C * * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 2 3+ (a) 3 3+ (a) 2 2 2 3+ (a) 3 3+ (a) 2 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C * * C C C C * * C C C C * * C * *
57 mb90f244 table 15 logical 2 instructions (long word) [6 instructions] for an explanation of (a) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 16 sign inversion instructions (byte/word) [6 instructions] for an explanation of (a), (b) and (c) and refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 17 absolute value instructions (byte/word/long word) [3 insturctions] table 18 normalize instructions (long word) [1 instruction] * : 5 when the contents of the accumulator are all zeroes, 5 + (r0) in all other cases. mnemonic # ~ b operation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ear xorl a, eam 2 2+ 2 2+ 2 2+ 5 6+ (a) 5 6+ (a) 5 6+ (a) 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 2 3+ (a) 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C * * negw a negw ear negw eam 1 2 2+ 2 2 3+ (a) 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C * * mnemonic # ~ b operation lh ah i s t n z v c rmw abs a absw a absl a 2 2 2 2 2 4 0 0 0 byte (a) ? absolute value (a) word (a) ? absolute value (a) long (a) ? absolute value (a) z C C C C C C C C C C C C C C * * * * * * * * * C C C C C C mnemonic # ~ b operation lh ah i s t n z v c rmw nrml a, r0 2 * 0 long (a) ? shifts to the position at which 1 was set first byte (r0) ? current shift count CCCC*CCCC C
mb90f244 58 table 19 shift instructions (byte/word/long word) [27 instructions] for an explanation of (a) and (b), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when r0 is 0, 3 + (r0) in all other cases. *2: 3 when r0 is 0, 4 + (r0) in all other cases. *3: 3 when imm8 is 0, 3 + (imm8) in all other cases. *4: 3 when imm8 is 0, 4 + (imm8) in all other cases. mnemonic # ~ b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 asr a, #imm8 lsr a, #imm8 lsl a, #imm8 2 2 2 2+ 2 2+ 2 2 2 3 3 3 2 2 2 3+ (a) 2 3+ (a) * 1 * 1 * 1 * 3 * 3 * 3 0 0 0 2 (b) 0 2 (b) 0 0 0 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) byte (a) ? arithmetic right barrel shift (a, imm8) byte (a) ? logical right barrel shift (a, imm8) byte (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C * * * * * * * * * * * * C C * * * * C C C C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 asrw a, #imm8 lsrw a, #imm8 lslw a, #imm8 1 1 1 2 2 2 3 3 3 2 2 2 * 1 * 1 * 1 * 3 * 3 * 3 0 0 0 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) word (a) ? arithmetic right barrel shift (a, imm8) word (a) ? logical right barrel shift (a, imm8) word (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * C * r * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 asrl a, #imm8 lsrl a, #imm8 lsll a, #imm8 2 2 2 3 3 3 * 2 * 2 * 2 * 4 * 4 * 4 0 0 0 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) long (a) ? arithmetic right shift (a, imm8) long (a) ? logical right barrel shift (a, imm8) long (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * C C C C C C * * * * * * C C C C C C
59 mb90f244 table 20 branch 1 instructions [31 instructions] for an explanation of (a), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when branching, 2 when not branching. *2: 3 (c) + (b) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) branch address. *7: save (long word) to stack. mnemonic # ~ b operation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 2 3 4+ (a) 3 4+ (a) 3 4 5+ (a) 5 5 7 8+ (a) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 ( (v) xor (n) ) or (z) = 1 ( (v) xor (n) ) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15 (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call linstruction word (pc) ? (ear) 0 to 15, (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15, (pcb) ? (eam) 16 to 23 word (pc) ? addr 0 to 15, (pcb) ? addr 16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90f244 60 table 21 branch 2 instructions [20 instructions] for an explanation of (b), (c) and (d), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 4 when branching, 3 when not branching *2: 5 when branching, 4 when not branching *3: 5 + (a) when branching, 4 + (a) when not branching *4: 6 + (a) when branching, 5 + (a) when not branching *5: 3 (b) + 2 (c) when an interrupt request is generated, 6 (c) when returning from the interrupt. *6: high-speed interrupt return instruction. when an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: return from stack (word) *8: return from stack (long word) mnemonic # ~ b operation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel cwbne ear, #imm16, rel cwbne eam, #imm16, rel dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti retiq * 6 link #imm8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 2 1 1 1 * 1 * 1 * 1 * 3 * 1 * 3 * 2 * 4 * 2 * 4 14 12 13 14 9 11 6 5 4 5 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) * 5 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when byte (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (ear) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * * C C C C C C C C C C C C C C s s s s * * C C C C C C C C C C C C C C C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * C C C C C C C C * * C C C C C C C C C C C * C * C C C C C C C C C C
61 mb90f244 table 22 other control instructions (byte/word/long word) [36 instructions] for an explanation of (a) and (c), refer to tables 4 and 5. *1: pcb, adb, ssb, usb, and spb: 1 cycle *4: pop count (c), or push count (c) dtb: 2 cycles *5: 3 when al is 0, 5 when al is not 0. dpr: 3 cycles *6: 4 when al is 0, 6 when al is not 0. *2: 3 + 4 (pop count) *7: 5 when al is 0, 7 when al is not 0. *3: 3 + 4 (push count) mnemonic # ~ b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a mov brg2, #imm8 nop adb dtb pcb spb ncc cmr movw spcu, #imm16 movw spcl, #imm16 setspc clrspc btscn a btscns a btscnda 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 3 3 3 * 3 3 3 3 * 2 9 3 3 2 2 3 2+ (a) 2 1+ (a) 3 3 * 1 1 2 1 1 1 1 1 1 1 2 2 2 2 * 5 * 6 * 7 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? (sp) +2 word (ah) ? ((sp)), (sp) ? (sp) +2 word (ps) ? ((sp)), (sp) ? (sp) +2 (rlst) ? ((sp)) , (sp) ? (sp) context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? ext (imm8) word (sp) ? imm16 byte (a) ? (brgl) byte (brg2) ? (a) byte (brg2) ? imm8 no operation prefix code for ad space access prefix code for dt space access prefix code for pc space access prefix code for sp space access prefix code for no flag change prefix code for the common register bank word (spcu) ? (imm16) word (spcl) ? (imm16) stack check operation enable stack check operation disable byte (a) ? position of 1 bit in word (a) byte (a) ? position of 1 bit in word (a) 2 byte (a) ? position of 1 bit in word (a) 4 C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C C z z z C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C * * * C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90f244 62 table 23 bit manipulation instructions [21 instructions] for an explanation of (b), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 5 when branching, 4 when not branching *2: 7 when condition is satisfied, 6 when not satisfied *3: undefined count *4: until condition is satisfied mnemonic # ~ b operation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 3 3 3 4 4 4 4 4 4 4 4 4 * 1 * 1 * 1 * 1 * 1 * 1 * 2 * 3 * 3 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 4 * 4 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
63 mb90f244 table 24 accumulator manipulation instructions (byte/word) [6 instructions] table 25 string instructions [10 instructions] m: rw0 value (counter value) *1: 3 when rw0 is 0, 2 + 6 (rw0) for count out, and 6n + 4 when match occurs *2: 4 when rw0 is 0, 2 + 6 (rw0) in any other case *3: (b) (rw0) *4: (b) n *5: (b) (rw0) *6: (c) (rw0) *7: (c) n *8: (c) (rw0) mnemonic # ~ b operation lh ah i s t n z v c rmw swap swapw ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 2 0 0 0 0 0 0 byte (a) 0 to 7 ? ? (a) 8 to 15 word (ah) ? ? (al) byte code extension word code extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ b operation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fils/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 5m +3 * 3 * 3 * 4 * 4 * 5 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval @ah+ C al, counter = rw0 byte retrieval @ahC C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 5m +3 * 6 * 6 * 7 * 7 * 8 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval @ah+ C al, counter = rw0 word retrieval @ahC C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
mb90f244 64 table 26 multiple data transfer instructions [18 instructions] *1: 5 + imm8 5, 256 times when imm8 is zero. *2: 5 + imm8 5 + (a), 256 times when imm8 is zero. *3: number of transfers (b) 2 *4: number of transfers (c) 2 *5: the bank register specified by bnk is the same as for the movs instruction. mnemonic # ~ b operation lh ah i s t n z v c rmw movm @a, @rli, #imm8 movm @a, eam, #imm8 movm addr16, @rli, #imm8 movm addr16, eam, #imm8 movmw @a, @rli, #imm8 movmw @a, eam, #imm8 movmw addr16, @rli, #imm8 movmw addr16, eam, #imm8 movm @rli, @a, #imm8 movm eam, @a, #imm8 movm @rli, addr16, #imm8 movm eam, addr16, #imm8 movmw @rli, @a, #imm8 movmw eam, @a, #imm8 movmw @rli, addr16, #imm8 movmw eam, addr16, #imm8 movm bnk : addr16, * 5 bnk : addr16, #imm8 movmw bnk : addr16, * 5 bnk : addr16, #imm8 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 7 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 1 * 3 * 3 * 3 * 3 * 4 * 4 * 4 * 4 * 3 * 3 * 3 * 3 * 4 * 4 * 4 * 4 * 3 * 4 multiple data trasfer byte ((a)) ? ((rli)) multiple data trasfer byte ((a)) ? (eam) multiple data trasfer byte (addr16) ? ((rli)) multiple data trasfer byte (addr16) ? (eam) multiple data trasfer word ((a)) ? ((rli)) multiple data trasfer word ((a)) ? (eam) multiple data trasfer word (addr16) ? ((rli)) multiple data trasfer word (addr16) ? (eam) multiple data trasfer byte ((rli)) ? ((a)) multiple data trasfer byte (eam) ? ((a)) multiple data transfer byte ((rli)) ? (addr16) multiple data transfer byte (eam) ? (addr16) multiple data trasfer word ((rli)) ? ((a)) multiple data trasfer word (eam) ? ((a)) multiple data transfer word ((rli)) ? (addr16) multiple data transfer word (eam) ? (addr16) multiple data transfer byte (bnk:addr16) ? (bnk:addr16) multiple data transfer word (bnk:addr16) ? (bnk:addr16) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
65 mb90f244 n ordering imformation part number package remarks MB90F244PFT-G 80-pin plastic tqfp (fpt-80p-m15)
mb90f244 66 n package dimensions 80-pin plastic tqfp (fpt-80p-m15) 1997 fujitsu limited f80028s-1c-1 details of "a" part c 0?~8? 0.45/0.75 (.018/.0295) 0.25(.010) 0.100.05(.004.002) (stand off height) 1.20(.047)max mounting height 1 20 40 21 60 41 80 61 12.000.10(.472.004)sq 14.000.20(.551.008)sq 0.50(.020) typ .009 ?.002 +.002 ?0.04 +0.05 0.22 0.08(.003) m 0.08(.003) "a" .006 ?.001 +.002 ?0.03 +0.05 0.145 dimensions in mm (inches)
67 mb90f244 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9807 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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